Emulating Petaflops Machines and Blue Gene
IEEE International Parallel and Distributed Processing Symposium (IPDPS) 2001
Publication Type: Paper
Repository URL:
Abstract
Petaflops-class computers, based on the current or foreseeable CMOS
generation, appear to be feasible in the near future. An emulator
for a petaflops-class programming environment is necessary to
facilitate offline development and debugging of applications, and
exploration of programming models. Such an emulator must be able to
run on large traditional parallel machines. This paper describes
the design and implementation of an emulator for a class of
petaflops machines. The machine parameters can be varied to cover a
variety of possible architectures within this class, although our
current implementation is influenced by (and is targeted to
emulate) an initial design of the Blue Gene Machine being developed
by IBM. Our implementation is based on Charm++, an object-based
message-driven parallel execution model, which allows emulation of
multiple Blue Gene nodes to a single physical processor. We
demonstrate the feasibility of our approach by emulating short
million-processor programs on less than a hundred processors of the
ASCI-Red machine.
TextRef
Neelam Saboo and Arun Kumar Singla and Joshua Mostkoff Unger and L. V. Kale,
"Emulating Petaflops Machines and Blue Gene", Workshop on Massively Parallel
Processing (IPDPS'01), San Francisco, CA, April 2001.
People
Research Areas