In the last several years, there has been an increased interest in using various accelerator technologies in the realm of high performance computing (HPC). Some of these technologies include the Cell processor (Cell), many integrated cores (MIC), the single chip cloud (SCC), field programmable gate arrays (FPGAs), and graphical processing units (GPUs). Quite a bit of effort has been put forth in harnessing the computing power of these technologies for more general purpose programming. However, making use of these technologies is typically considered hard for various reasons, including their parallel nature and the architecture-specific details involved in programming them.
In this work, we would like to explore (1) how the various pieces of accelerator hardware can be abstracted within a programming model and (2) how an underlying runtime system can assist programmers in making use of accelerators. In other words, how can we make accelerators more accessible to programmers and allow them to focus on the problem at hand, rather than focusing on the hardware itself? What role can/should runtime systems play in making accelerator technologies more accessible to programmers?