@5333.ADF - National Instruments MC-GPIB IEEE-488 IF 
320738.pdf   MC-GPIB and the NI-488.2 Software for DOS 
320739.pdf   MC-GPIB and the NI-488.2 Software for Windows (3.1x)
/320608.pdf   MC-GPIB and NI-488.2M for OS/2 

The NAT4882 controller chip is fully compatible with the IEEE 488.2 standard. The Turbo488 performance-enhancing ASIC boosts GPIB read
and write transfers to rates exceeding 1 Mbytes/s.

Setting the Shield Ground Configuration Jumper W1
The MC-GPIB board is set at the factory with the jumper in place to connect the logic ground of the MC-GPIB board to its shield ground. This  onfiguration minimizes EMI emissions.

If you are installing one MC-GPIB board, the software assigns it as gpib0. If you are installing more than one board, the board in the lowest-numbered slot is gpib0, the board in the next lowest-numbered slot is gpib1, and so on.

Characteristic Specification
Maximum GPIB Transfer Rates (DOS)
Reads 800 kbytes/s
Writes 1.1 Mbytes/s
Power Requirement +5 VDC 1.0 A Typ  1.6 A Max 

I/O Base Address for MC-GPIB
     <"IOBASE 0E00" (0e00-00fff)>, 1E00 (1e00-01fff), 2E00 (2e00-02fff), 3E00 (3e00-03fff), 4E00 (4e00-04fff), 5E00 (5e00-05fff), 6E00 (6e00-06fff), 7E00 (7e00-07fff), 8E00 (8e00-08fff), 9E00 (9e00-09fff), AE00 (ae00-0afff),BE00 (be00-0bfff), CE00 (ce00-0cfff), DE00 (de00-0dfff), EE00 (ee00-0efff), FE00 (fe00-0ffff)

Interrupt Level for MC-GPIB
        <"Int_3">, 5, 10, 11, 15, Not Used

Arbitration Level for MC-GPIB
        <"Level_0">, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, No DMA

Fairness On/Off
   This controls whether the adapter will release control of the bus when it has been using it exclusively.
         <"On">, Off