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7007-N40 IBM RS/6000 Model N40 7008 Overview IBM RS/6000 7008 Overview IBM RS/6000 M2A M20 7009 User's Guide 80-120MHz MCA Deskside 7009 Overview IBM RS/6000 Compact Server Compact Server Model C10 Compact Server Model C20 7010 Overview IBM RS/6000 120 130 140 150 160 7011 User's Guide 33-80MHz MCA Wrkstn 7011 Overview IBM RS/6000 22W 220 23S 23T 23W 230 25E 25F 25S 25T 25W 250 7012 20-200MHz MCA Desktop 300 Series User's Guide G Series User's Guide 7012 Overview IBM RS/6000 G02 G30 Enterprise Server Model G40 32H 320 34H 340 350 355 36T 360 365 37T 370 375 380 39H 390 Workstation/Server Model 397 7013 20-200MHz MCA Deskside J Series User's Guide 7013 Overview IBM RS/6000 J01 J30 Enterprise Server Model J40 Enterprise Server Model J50 Enterprise Server S70 Advanced Model S7A Enterprise Server Upgrade Model S70 52H 520 53H 530 540 55L 550 560 570 58H 580 59H 590 591 Deskside Server Model 595 7014 Overview IBM RS/6000 S00 T00 T42 7015 25-200MHz MCA Rack 7015 Overview IBM RS/6000 R00 R10 R20 R21 R24 R3U R30 R4U Enterprise Server Model R40 R5U Enterprise Server Model R50 Enterprise Server S70 Advanced Model S7A Enterprise Server Upgrade Model S70 930 950 97B 970 98B 980 99J 99K 990 7017 125-450MHz PCI Enterprise 7024 100-233MHz PCI Deskside 7025 166-375MHz PCI Wrkstn/WrkGp Svr 7026 166-500MHz PCI Wrkgp Svr- Rack 7030 MCA 7030 Overview IBM RS/6000 3AT 3BT 3CT Workstation Upgrade Model 397 7043 166-375MHz PCI Wrkstn/Wrkgp Svrs 7044 333-400MHz PCI Wrkstn/Wrkgp Svrs 7046 375MHz PCI Wrkgp Svr- Rack SP/1,2 All Node Types (???) POWER2 TECHNOLOGY The POWER2 technology implemented in this machine is a next-generation, multi-chip RISC processor implementation of the POWER Architecture (TM). The processor chips are fabricated in .5-micron, 4-level metal/1-level polysilicon CMOS 4S and are packaged on a single, multi-chip ceramic module. Like the POWER2 technology introduced in September 1993, the primary features of the system include: o 32KB, two-way set associative instruction cache and a multi-port, 128KB four-way set associative data cache. o Dual fixed-point execution units and dual floating-point, multiply-add-divide units. The architecture provides a quad word floating-point load/store instruction, convert-to-integer instruction, square root instruction, new address translation, and a new interrupt structure. o Hardware performance monitors accessible by software. o Memory interface is four-words wide and supports memory up to 2GB (memory interface on Models 58H and 590 is eight-words wide). o Binary-compatible with previous IBM RISC System/6000 systems. LEVEL 2 (L2) CACHE
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