[automerger skipped] Merge Android 24Q1 Release (ab/11220357) am: 3f66ebf163 -s ours
am skip reason: Merged-In I5bf4143db67448d5ed2c581c61985f7e2ac21ddc with SHA-1 1357848058 is already in history
Original change: https://googleplex-android-review.googlesource.com/c/platform/hardware/google/graphics/zuma/+/25974135
Change-Id: I8e172229961a7e64991aeac2fb9d6e5aeab4d870
Signed-off-by: Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com>
diff --git a/libhwc2.1/Android.mk b/libhwc2.1/Android.mk
index c704838..083af9b 100644
--- a/libhwc2.1/Android.mk
+++ b/libhwc2.1/Android.mk
@@ -27,6 +27,7 @@
../../gs101/libhwc2.1/libdisplayinterface/ExynosDisplayDrmInterfaceModule.cpp \
../../gs201/libhwc2.1/libdisplayinterface/ExynosDisplayDrmInterfaceModule.cpp \
../../zuma/libhwc2.1/libdisplayinterface/ExynosDisplayDrmInterfaceModule.cpp \
+ ../../gs101/libhwc2.1/libcolormanager/ColorManager.cpp \
../../zuma/libhwc2.1/libcolormanager/DisplayColorModule.cpp \
../../zuma/libhwc2.1/libdevice/ExynosDeviceModule.cpp \
../../zuma/libhwc2.1/libdevice/HistogramController.cpp
diff --git a/libhwc2.1/ExynosHWCModule.h b/libhwc2.1/ExynosHWCModule.h
index 29412f2..97d16fb 100644
--- a/libhwc2.1/ExynosHWCModule.h
+++ b/libhwc2.1/ExynosHWCModule.h
@@ -88,50 +88,50 @@
// Zuma has total 14 Layers
// DPP0(IDMA_GFS0) in DPUF0 is connected with AXI0 port
- {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS0", 0, 0, HWC_DISPLAY_PRIMARY_BIT,
- static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI0)},
+ {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS0", 0, 0, HWC_RESERVE_DISPLAY_MAIN_BIT,
+ static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI0)},
// DPP1(IDMA_VGRFS0) in DPUF0 is connected with AXI0 port
- {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS0", 0, 0, HWC_DISPLAY_PRIMARY_BIT,
- static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI0)},
+ {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS0", 0, 0, HWC_RESERVE_DISPLAY_MAIN_BIT,
+ static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI0)},
// DPP2(IDMA_GFS1) in DPUF0 is connected with AXI0 port
- {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS1", 1, 0, HWC_DISPLAY_PRIMARY_BIT,
- static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI0)},
+ {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS1", 1, 0, HWC_RESERVE_DISPLAY_MAIN_BIT,
+ static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI0)},
// DPP3(IDMA_VGRFS1) in DPUF0 is connected with AXI0 port
- {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS1", 1, 0, HWC_DISPLAY_PRIMARY_BIT,
- static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI0)},
+ {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS1", 1, 0, HWC_RESERVE_DISPLAY_MAIN_BIT,
+ static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI0)},
// DPP4(IDMA_GFS2) in DPUF0 is connected with AXI1 port
- {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS2", 2, 0, HWC_DISPLAY_PRIMARY_BIT,
- static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI1)},
+ {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS2", 2, 0, HWC_RESERVE_DISPLAY_MINOR_BIT,
+ static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI1)},
// DPP5(IDMA_VGRFS2) in DPUF0 is connected with AXI1 port
- {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS2", 2, 0, HWC_DISPLAY_PRIMARY_BIT,
- static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI1)},
+ {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS2", 2, 0, HWC_RESERVE_DISPLAY_MAIN_BIT,
+ static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI1)},
// DPP6(IDMA_GFS3) in DPUF0 is connected with AXI1 port
- {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS3", 3, 0, HWC_DISPLAY_PRIMARY_BIT,
- static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI1)},
+ {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS3", 3, 0, HWC_RESERVE_DISPLAY_MINOR_BIT,
+ static_cast<uint32_t>(DPUF0), static_cast<uint32_t>(AXI1)},
// DPP7(IDMA_GFS4) in DPUF1 is connected with AXI1 port
- {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS4", 4, 0, HWC_DISPLAY_SECONDARY_BIT,
- static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)},
+ {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS4", 4, 0, HWC_RESERVE_DISPLAY_MAIN_BIT,
+ static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)},
// DPP8(IDMA_VGRFS3) in DPUF1 is connected with AXI1 port
- {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS3", 3, 0, HWC_DISPLAY_SECONDARY_BIT,
- static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)},
+ {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS3", 3, 0, HWC_RESERVE_DISPLAY_MAIN_BIT,
+ static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)},
// DPP9(IDMA_GFS5) in DPUF1 is connected with AXI1 port
- {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS5", 5, 0, HWC_DISPLAY_SECONDARY_BIT,
- static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)},
+ {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS5", 5, 0, HWC_RESERVE_DISPLAY_MINOR_BIT,
+ static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)},
// DPP10(IDMA_VGRFS4) in DPUF1 is connected with AXI1 port
- {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS4", 4, 0, HWC_DISPLAY_SECONDARY_BIT,
- static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)},
+ {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS4", 4, 0, HWC_RESERVE_DISPLAY_MAIN_BIT,
+ static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI1)},
// DPP11(IDMA_GFS6) in DPUF1 is connected with AXI0 port
- {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS6", 6, 0, HWC_DISPLAY_EXTERNAL_BIT,
- static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI0)},
+ {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS6", 6, 0, HWC_RESERVE_DISPLAY_MINOR_BIT,
+ static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI0)},
// DPP12(IDMA_VGRFS5) in DPUF1 is connected with AXI0 port
- {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS5", 5, 0, HWC_DISPLAY_EXTERNAL_BIT,
- static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI0)},
+ {MPP_DPP_VGRFS, MPP_LOGICAL_DPP_VGRFS, "DPP_VGRFS5", 5, 0, HWC_RESERVE_DISPLAY_MINOR_BIT,
+ static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI0)},
// DPP13(IDMA_GFS7) in DPUF1 is connected with AXI0 port
- {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS7", 7, 0, HWC_DISPLAY_EXTERNAL_BIT,
- static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI0)},
+ {MPP_DPP_GFS, MPP_LOGICAL_DPP_GFS, "DPP_GFS7", 7, 0, HWC_RESERVE_DISPLAY_MINOR_BIT,
+ static_cast<uint32_t>(DPUF1), static_cast<uint32_t>(AXI0)},
};
static const std::array<exynos_display_t, 3> AVAILABLE_DISPLAY_UNITS = {{
@@ -150,25 +150,20 @@
tdm_attr_t attr;
DPUblockId_t DPUBlockNo;
AXIPortId_t axiId;
- int dispType;
ConstraintRev_t constraintRev;
public:
- HWResourceIndexes(const tdm_attr_t &_attr, const DPUblockId_t &_DPUBlockNo,
- const AXIPortId_t &_axiId, const int &_dispType,
- const ConstraintRev_t &_constraintRev)
+ HWResourceIndexes(const tdm_attr_t& _attr, const DPUblockId_t& _DPUBlockNo,
+ const AXIPortId_t& _axiId, const ConstraintRev_t& _constraintRev)
: attr(_attr),
DPUBlockNo(_DPUBlockNo),
axiId(_axiId),
- dispType(_dispType),
constraintRev(_constraintRev) {}
bool operator<(const HWResourceIndexes& rhs) const {
if (attr != rhs.attr) return attr < rhs.attr;
if (DPUBlockNo != rhs.DPUBlockNo) return DPUBlockNo < rhs.DPUBlockNo;
- if (dispType != rhs.dispType) return dispType < rhs.dispType;
-
if (axiId != AXI_DONT_CARE && rhs.axiId != AXI_DONT_CARE && axiId != rhs.axiId)
return axiId < rhs.axiId;
@@ -178,15 +173,16 @@
}
String8 toString8() const {
String8 log;
- log.appendFormat("attr=%d,DPUBlockNo=%d,axiId=%d,dispType=%d,constraintRev=%d", attr,
- DPUBlockNo, axiId, dispType, constraintRev);
+ log.appendFormat("attr=%d,DPUBlockNo=%d,axiId=%d,constraintRev=%d", attr, DPUBlockNo,
+ axiId, constraintRev);
return log;
}
};
typedef struct HWResourceAmounts {
- int maxAssignedAmount;
- int totalAmount;
+ int mainAmount;
+ int minorAmount;
+ int total;
} HWResourceAmounts_t;
/* Note :
@@ -194,144 +190,31 @@
* Primary amount = total - others */
const std::map<HWResourceIndexes, HWResourceAmounts_t> HWResourceTables = {
- {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY,
- CONSTRAINT_NONE),
- {80, 80}},
- {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL,
- CONSTRAINT_NONE),
- {0, 80}},
- {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
- CONSTRAINT_NONE),
- {0, 80}},
- {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY,
- CONSTRAINT_NONE),
- {80, 80}},
- {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL,
- CONSTRAINT_NONE),
- {80, 80}},
- {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
- CONSTRAINT_NONE),
- {80, 80}},
-
- {HWResourceIndexes(TDM_ATTR_SCALE, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY,
- CONSTRAINT_NONE),
- {2, 2}},
- {HWResourceIndexes(TDM_ATTR_SCALE, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL,
- CONSTRAINT_NONE),
- {0, 2}},
- {HWResourceIndexes(TDM_ATTR_SCALE, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
- CONSTRAINT_NONE),
- {0, 2}},
- {HWResourceIndexes(TDM_ATTR_SCALE, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY,
- CONSTRAINT_NONE),
- {2, 2}},
- {HWResourceIndexes(TDM_ATTR_SCALE, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL,
- CONSTRAINT_NONE),
- {2, 2}},
- {HWResourceIndexes(TDM_ATTR_SCALE, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
- CONSTRAINT_NONE),
- {2, 2}},
-
- {HWResourceIndexes(TDM_ATTR_SBWC, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY,
- CONSTRAINT_NONE),
- {2, 2}},
- {HWResourceIndexes(TDM_ATTR_SBWC, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL,
- CONSTRAINT_NONE),
- {0, 2}},
- {HWResourceIndexes(TDM_ATTR_SBWC, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
- CONSTRAINT_NONE),
- {0, 2}},
- {HWResourceIndexes(TDM_ATTR_SBWC, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY,
- CONSTRAINT_NONE),
- {2, 2}},
- {HWResourceIndexes(TDM_ATTR_SBWC, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL,
- CONSTRAINT_NONE),
- {2, 2}},
- {HWResourceIndexes(TDM_ATTR_SBWC, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
- CONSTRAINT_NONE),
- {2, 2}},
-
- {HWResourceIndexes(TDM_ATTR_AFBC, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY,
- CONSTRAINT_NONE),
- {4, 4}},
- {HWResourceIndexes(TDM_ATTR_AFBC, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL,
- CONSTRAINT_NONE),
- {0, 4}},
- {HWResourceIndexes(TDM_ATTR_AFBC, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
- CONSTRAINT_NONE),
- {0, 4}},
- {HWResourceIndexes(TDM_ATTR_AFBC, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY,
- CONSTRAINT_NONE),
- {4, 4}},
- {HWResourceIndexes(TDM_ATTR_AFBC, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL,
- CONSTRAINT_NONE),
- {4, 4}},
- {HWResourceIndexes(TDM_ATTR_AFBC, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
- CONSTRAINT_NONE),
- {4, 4}},
-
- {HWResourceIndexes(TDM_ATTR_ITP, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY,
- CONSTRAINT_NONE),
- {4, 4}},
- {HWResourceIndexes(TDM_ATTR_ITP, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL,
- CONSTRAINT_NONE),
- {0, 4}},
- {HWResourceIndexes(TDM_ATTR_ITP, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
- CONSTRAINT_NONE),
- {0, 4}},
- {HWResourceIndexes(TDM_ATTR_ITP, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY,
- CONSTRAINT_NONE),
- {4, 4}},
- {HWResourceIndexes(TDM_ATTR_ITP, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL,
- CONSTRAINT_NONE),
- {4, 4}},
- {HWResourceIndexes(TDM_ATTR_ITP, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
- CONSTRAINT_NONE),
- {4, 4}},
-
- {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY,
- CONSTRAINT_NONE),
- {2, 2}},
- {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL,
- CONSTRAINT_NONE),
- {0, 2}},
- {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
- CONSTRAINT_NONE),
- {0, 2}},
- {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY,
- CONSTRAINT_NONE),
- {2, 2}},
- {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL,
- CONSTRAINT_NONE),
- {2, 2}},
- {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL,
- CONSTRAINT_NONE),
- {2, 2}},
-
- {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY, CONSTRAINT_A0),
- {2, 2}},
- {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL, CONSTRAINT_A0),
- {0, 2}},
- {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL, CONSTRAINT_A0),
- {0, 2}},
- {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_PRIMARY, CONSTRAINT_A0),
- {2, 2}},
- {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_EXTERNAL, CONSTRAINT_A0),
- {2, 2}},
- {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI_DONT_CARE, HWC_DISPLAY_VIRTUAL, CONSTRAINT_A0),
- {2, 2}},
- {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI0, HWC_DISPLAY_PRIMARY, CONSTRAINT_B0), {2, 2}},
- {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI0, HWC_DISPLAY_EXTERNAL, CONSTRAINT_B0), {0, 2}},
- {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI0, HWC_DISPLAY_VIRTUAL, CONSTRAINT_B0), {0, 2}},
- {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI1, HWC_DISPLAY_PRIMARY, CONSTRAINT_B0), {2, 2}},
- {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI1, HWC_DISPLAY_EXTERNAL, CONSTRAINT_B0), {0, 2}},
- {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI1, HWC_DISPLAY_VIRTUAL, CONSTRAINT_B0), {0, 2}},
- {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI0, HWC_DISPLAY_PRIMARY, CONSTRAINT_B0), {2, 2}},
- {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI0, HWC_DISPLAY_EXTERNAL, CONSTRAINT_B0), {2, 2}},
- {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI0, HWC_DISPLAY_VIRTUAL, CONSTRAINT_B0), {2, 2}},
- {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI1, HWC_DISPLAY_PRIMARY, CONSTRAINT_B0), {2, 2}},
- {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI1, HWC_DISPLAY_EXTERNAL, CONSTRAINT_B0), {2, 2}},
- {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI1, HWC_DISPLAY_VIRTUAL, CONSTRAINT_B0), {2, 2}},
+ // SRAM
+ {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF0, AXI_DONT_CARE, CONSTRAINT_NONE), {50, 30, 80}},
+ {HWResourceIndexes(TDM_ATTR_SRAM_AMOUNT, DPUF1, AXI_DONT_CARE, CONSTRAINT_NONE), {50, 30, 80}},
+ // SCALE
+ {HWResourceIndexes(TDM_ATTR_SCALE, DPUF0, AXI_DONT_CARE, CONSTRAINT_NONE), {2, 0, 2}},
+ {HWResourceIndexes(TDM_ATTR_SCALE, DPUF1, AXI_DONT_CARE, CONSTRAINT_NONE), {1, 1, 2}},
+ // SBWC
+ {HWResourceIndexes(TDM_ATTR_SBWC, DPUF0, AXI_DONT_CARE, CONSTRAINT_NONE), {2, 0, 2}},
+ {HWResourceIndexes(TDM_ATTR_SBWC, DPUF1, AXI_DONT_CARE, CONSTRAINT_NONE), {0, 2, 2}},
+ // AFBC
+ {HWResourceIndexes(TDM_ATTR_AFBC, DPUF0, AXI_DONT_CARE, CONSTRAINT_NONE), {3, 1, 4}},
+ {HWResourceIndexes(TDM_ATTR_AFBC, DPUF1, AXI_DONT_CARE, CONSTRAINT_NONE), {1, 3, 4}},
+ // ITP
+ {HWResourceIndexes(TDM_ATTR_ITP, DPUF0, AXI_DONT_CARE, CONSTRAINT_NONE), {3, 1, 4}},
+ {HWResourceIndexes(TDM_ATTR_ITP, DPUF1, AXI_DONT_CARE, CONSTRAINT_NONE), {1, 3, 4}},
+ // ROT_90
+ {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF0, AXI_DONT_CARE, CONSTRAINT_NONE), {1, 1, 2}},
+ {HWResourceIndexes(TDM_ATTR_ROT_90, DPUF1, AXI_DONT_CARE, CONSTRAINT_NONE), {1, 1, 2}},
+ // WCG
+ {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI_DONT_CARE, CONSTRAINT_A0), {2, 0, 2}},
+ {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI_DONT_CARE, CONSTRAINT_A0), {0, 2, 2}},
+ {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI0, CONSTRAINT_B0), {2, 0, 2}},
+ {HWResourceIndexes(TDM_ATTR_WCG, DPUF0, AXI1, CONSTRAINT_B0), {2, 0, 2}},
+ {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI0, CONSTRAINT_B0), {0, 2, 2}},
+ {HWResourceIndexes(TDM_ATTR_WCG, DPUF1, AXI1, CONSTRAINT_B0), {0, 2, 2}},
};
typedef enum lbWidthIndex {
diff --git a/libhwc2.1/libcolormanager/ColorManager.h b/libhwc2.1/libcolormanager/ColorManager.h
new file mode 100644
index 0000000..c60f41a
--- /dev/null
+++ b/libhwc2.1/libcolormanager/ColorManager.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2023 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#pragma once
+
+#include "../../../gs101/libhwc2.1/libcolormanager/ColorManager.h"
diff --git a/libhwc2.1/libmaindisplay/ExynosPrimaryDisplayModule.cpp b/libhwc2.1/libmaindisplay/ExynosPrimaryDisplayModule.cpp
index b5bb83a..a49dc3c 100644
--- a/libhwc2.1/libmaindisplay/ExynosPrimaryDisplayModule.cpp
+++ b/libhwc2.1/libmaindisplay/ExynosPrimaryDisplayModule.cpp
@@ -253,7 +253,9 @@
int count = 0;
auto checkPreblending = [&](const int idx, ExynosMPPSource* mppSrc) -> int {
- auto& dpp = getDppForLayer(mppSrc);
+ auto* colorManager = getColorManager();
+ if (!colorManager) return false;
+ auto& dpp = colorManager->getDppForLayer(mppSrc);
mppSrc->mNeedPreblending =
dpp.EotfLut().enable | dpp.Gm().enable | dpp.Dtm().enable | dpp.OetfLut().enable;
if (hwcCheckDebugMessages(eDebugTDM)) {
diff --git a/libhwc2.1/libresource/ExynosResourceManagerModule.cpp b/libhwc2.1/libresource/ExynosResourceManagerModule.cpp
index faf52af..0428350 100644
--- a/libhwc2.1/libresource/ExynosResourceManagerModule.cpp
+++ b/libhwc2.1/libresource/ExynosResourceManagerModule.cpp
@@ -150,78 +150,65 @@
return true;
}
-void ExynosResourceManagerModule::setupHWResource(const tdm_attr_t &tdmAttrId, const String8 &name,
- const DPUblockId_t &blkId,
- const AXIPortId_t &axiId, ExynosDisplay *display,
- ExynosDisplay *addedDisplay,
- const ConstraintRev_t &constraintsRev) {
- const int32_t dispType = display->mType;
- const auto &resourceIdx = HWResourceIndexes(tdmAttrId, blkId, axiId, dispType, constraintsRev);
+void ExynosResourceManagerModule::setupHWResource(const tdm_attr_t& tdmAttrId, const String8& name,
+ const DPUblockId_t& blkId,
+ const AXIPortId_t& axiId, ExynosDisplay* mainDisp,
+ ExynosDisplay* minorDisp,
+ const ConstraintRev_t& constraintsRev) {
+ const auto& resourceIdx = HWResourceIndexes(tdmAttrId, blkId, axiId, constraintsRev);
const auto &iter = mHWResourceTables->find(resourceIdx);
if (iter != mHWResourceTables->end()) {
auto &hwResource = iter->second;
const auto &TDMInfoIdx = (HWAttrs.at(tdmAttrId).loadSharing == LS_DPUF)
? std::make_pair(blkId, AXI_DONT_CARE)
: std::make_pair(blkId, axiId);
- uint32_t amount = (addedDisplay == nullptr) ? hwResource.maxAssignedAmount
- : hwResource.totalAmount -
- addedDisplay->mDisplayTDMInfo[TDMInfoIdx]
- .getAvailableAmount(tdmAttrId)
- .totalAmount;
- display->mDisplayTDMInfo[TDMInfoIdx].initTDMInfo(DisplayTDMInfo::ResourceAmount_t{amount},
- tdmAttrId);
- if (addedDisplay == nullptr) {
- HDEBUGLOGD(eDebugTDM, "(%s=>%s) : %s amount is updated to %d",
- resourceIdx.toString8().c_str(), iter->first.toString8().c_str(),
- name.c_str(), amount);
- } else {
- HDEBUGLOGD(eDebugTDM, "(%s=>%s) : hwResource.totalAmount=%d %s amount is updated to %d",
- resourceIdx.toString8().c_str(), iter->first.toString8().c_str(),
- hwResource.totalAmount, name.c_str(), amount);
+ if (mainDisp != nullptr) {
+ const uint32_t mainAmount = (minorDisp != nullptr)
+ ? hwResource.mainAmount
+ : hwResource.mainAmount + hwResource.minorAmount;
+ mainDisp->mDisplayTDMInfo[TDMInfoIdx]
+ .initTDMInfo(DisplayTDMInfo::ResourceAmount_t{mainAmount}, tdmAttrId);
+ }
+ if (minorDisp != nullptr) {
+ const uint32_t minorAmount = hwResource.minorAmount;
+ minorDisp->mDisplayTDMInfo[TDMInfoIdx]
+ .initTDMInfo(DisplayTDMInfo::ResourceAmount_t{minorAmount}, tdmAttrId);
}
} else {
ALOGW("(%s): cannot find resource for %s", resourceIdx.toString8().c_str(), name.c_str());
}
}
-uint32_t ExynosResourceManagerModule::setDisplaysTDMInfo()
-{
- ExynosDisplay *addedDisplay = nullptr;
-
+uint32_t ExynosResourceManagerModule::setDisplaysTDMInfo(ExynosDisplay* mainDisp,
+ ExynosDisplay* minorDisp) {
/*
- * Checking display connections,
- * Assume that WFD and External are not connected at the same time
- * If non-primary display is connected, primary display's HW resource is looted
+ * Update main/minor display resource amount
+ * If only one display exists, all TDM resources are allocated for the only display.
*/
- for (auto &display : mDisplays) {
- if (display->mType == HWC_DISPLAY_PRIMARY) continue;
- if (display->isEnabled()) {
- addedDisplay = display;
- break;
- }
- }
-
- /*
- * Update Primary's resource amount. primary = total - loot(other display's HW resource)
- * Other's aready defined at initDisplaysTDMInfo()
- */
- ExynosDisplay *primaryDisplay = getDisplay(getDisplayId(HWC_DISPLAY_PRIMARY, 0));
for (auto attr = HWAttrs.begin(); attr != HWAttrs.end(); attr++) {
for (auto blockId = DPUBlocks.begin(); blockId != DPUBlocks.end(); blockId++) {
if (attr->second.loadSharing == LS_DPUF) {
setupHWResource(attr->first, attr->second.name, blockId->first, AXI_DONT_CARE,
- primaryDisplay, addedDisplay, mConstraintRev);
+ mainDisp, minorDisp, mConstraintRev);
} else if (attr->second.loadSharing == LS_DPUF_AXI) {
for (auto axi = AXIPorts.begin(); axi != AXIPorts.end(); ++axi) {
setupHWResource(attr->first, attr->second.name, blockId->first, axi->first,
- primaryDisplay, addedDisplay, mConstraintRev);
+ mainDisp, minorDisp, mConstraintRev);
}
}
+ else {
+ ALOGE("%s attr[%s] wrong load sharing=%d", __func__, attr->second.name.c_str(),
+ attr->second.loadSharing);
+ return BAD_TYPE;
+ }
}
}
if (hwcCheckDebugMessages(eDebugTDM)) {
for (auto &display : mDisplays) {
+ if (!(display->mPlugState == true && display->mPowerModeState.has_value() &&
+ display->mPowerModeState.value() != (hwc2_power_mode_t)HWC_POWER_MODE_OFF))
+ continue;
for (auto attr = HWAttrs.begin(); attr != HWAttrs.end(); attr++) {
for (auto blockId = DPUBlocks.begin(); blockId != DPUBlocks.end(); blockId++) {
if (attr->second.loadSharing == LS_DPUF) {
@@ -230,7 +217,7 @@
.getAvailableAmount(attr->first)
.totalAmount;
HDEBUGLOGD(eDebugTDM, "%s : [%s] display:%d,block:%d, amount : %d(%s)",
- __func__, attr->second.name.c_str(), display->mType,
+ __func__, attr->second.name.c_str(), display->mDisplayId,
blockId->first, amount,
display->isEnabled() ? "used" : "not used");
} else {
@@ -251,32 +238,7 @@
}
}
- return 0;
-}
-
-uint32_t ExynosResourceManagerModule::initDisplaysTDMInfo()
-{
- /*
- * Initialize as predefined value at table
- * Primary's resource will be changed at setDisplaysTDMInfo() function
- */
- for (auto &display : mDisplays) {
- for (auto attr = HWAttrs.begin(); attr != HWAttrs.end(); attr++) {
- for (auto blockId = DPUBlocks.begin(); blockId != DPUBlocks.end(); blockId++) {
- if (attr->second.loadSharing == LS_DPUF) {
- setupHWResource(attr->first, attr->second.name, blockId->first, AXI_DONT_CARE,
- display, nullptr, mConstraintRev);
- } else if (attr->second.loadSharing == LS_DPUF_AXI) {
- for (auto axi = AXIPorts.begin(); axi != AXIPorts.end(); ++axi) {
- setupHWResource(attr->first, attr->second.name, blockId->first, axi->first,
- display, nullptr, mConstraintRev);
- }
- }
- }
- }
- }
-
- return 0;
+ return NO_ERROR;
}
uint32_t getSramAmount(tdm_attr_t attr, uint32_t formatProperty, lbWidthIndex_t widthIndex) {
@@ -615,3 +577,15 @@
return 0;
}
+
+bool ExynosResourceManagerModule::isAssignable(ExynosMPP* candidateMPP, ExynosDisplay* display,
+ struct exynos_image& src, struct exynos_image& dst,
+ ExynosMPPSource* mppSrc) {
+ if (display != nullptr && candidateMPP != nullptr &&
+ display->mType == HWC_DISPLAY_EXTERNAL &&
+ !(candidateMPP->mPhysicalType == MPP_DPP_VGRFS && candidateMPP->mPhysicalIndex == 0)) {
+ return false;
+ }
+ return gs201::ExynosResourceManagerModule::isAssignable(candidateMPP, display, src, dst,
+ mppSrc);
+}
diff --git a/libhwc2.1/libresource/ExynosResourceManagerModule.h b/libhwc2.1/libresource/ExynosResourceManagerModule.h
index cf6c4fe..e9ab5ad 100644
--- a/libhwc2.1/libresource/ExynosResourceManagerModule.h
+++ b/libhwc2.1/libresource/ExynosResourceManagerModule.h
@@ -29,8 +29,7 @@
/* TDM (Time-Division Multiplexing) based Resource Management */
virtual bool isHWResourceAvailable(ExynosDisplay *display, ExynosMPP *currentMPP,
ExynosMPPSource *mppSrc);
- virtual uint32_t setDisplaysTDMInfo();
- virtual uint32_t initDisplaysTDMInfo();
+ virtual uint32_t setDisplaysTDMInfo(ExynosDisplay* mainDisp, ExynosDisplay* minorDisp);
virtual uint32_t calculateHWResourceAmount(ExynosDisplay *display, ExynosMPPSource *mppSrc);
virtual int32_t otfMppReordering(ExynosDisplay *display, ExynosMPPVector &otfMPPs,
struct exynos_image &src, struct exynos_image &dst);
@@ -45,10 +44,13 @@
bool checkTDMResource(ExynosDisplay *display, ExynosMPP *currentMPP,
ExynosMPPSource *mppSrc);
const std::map<HWResourceIndexes, HWResourceAmounts_t> *mHWResourceTables = nullptr;
- void setupHWResource(const tdm_attr_t &tdmAttrId, const String8 &name,
- const DPUblockId_t &blkId, const AXIPortId_t &axiId,
- ExynosDisplay *display, ExynosDisplay *addedDisplay,
- const ConstraintRev_t &constraintsRev);
+ void setupHWResource(const tdm_attr_t& tdmAttrId, const String8& name,
+ const DPUblockId_t& blkId, const AXIPortId_t& axiId,
+ ExynosDisplay* mainDisp, ExynosDisplay* minorDisp,
+ const ConstraintRev_t& constraintsRev);
+ virtual bool isAssignable(ExynosMPP* candidateMPP, ExynosDisplay* display,
+ struct exynos_image& src, struct exynos_image& dst,
+ ExynosMPPSource* mppSrc);
private:
ConstraintRev_t mConstraintRev;
