Programmable packet scheduling at line rate
Proceedings of the 2016 ACM SIGCOMM Conference, 2016•dl.acm.org
Switches today provide a small menu of scheduling algorithms. While we can tweak
scheduling parameters, we cannot modify algorithmic logic, or add a completely new
algorithm, after the switch has been designed. This paper presents a design for a {\em
programmable} packet scheduler, which allows scheduling algorithms---potentially
algorithms that are unknown today---to be programmed into a switch without requiring
hardware redesign. Our design uses the property that scheduling algorithms make two …
scheduling parameters, we cannot modify algorithmic logic, or add a completely new
algorithm, after the switch has been designed. This paper presents a design for a {\em
programmable} packet scheduler, which allows scheduling algorithms---potentially
algorithms that are unknown today---to be programmed into a switch without requiring
hardware redesign. Our design uses the property that scheduling algorithms make two …
Switches today provide a small menu of scheduling algorithms. While we can tweak scheduling parameters, we cannot modify algorithmic logic, or add a completely new algorithm, after the switch has been designed. This paper presents a design for a {\em programmable} packet scheduler, which allows scheduling algorithms---potentially algorithms that are unknown today---to be programmed into a switch without requiring hardware redesign.
Our design uses the property that scheduling algorithms make two decisions: in what order to schedule packets and when to schedule them. Further, we observe that in many scheduling algorithms, definitive decisions on these two questions can be made when packets are enqueued. We use these observations to build a programmable scheduler using a single abstraction: the push-in first-out queue (PIFO), a priority queue that maintains the scheduling order or time.
We show that a PIFO-based scheduler lets us program a wide variety of scheduling algorithms. We present a hardware design for this scheduler for a 64-port 10 Gbit/s shared-memory (output-queued) switch. Our design costs an additional 4% in chip area. In return, it lets us program many sophisticated algorithms, such as a 5-level hierarchical scheduler with programmable decisions at each level.
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