It is shown that counter circuits can always be designed to be testable with either eight or ten tests, irrespective of the input size.

1986/10/01 · This report investigates the testability of a class of circuits, called counters, that perforin the addition of sets of input bits of equal ...

Title: On the C-Testability of Generalized Counters ; Author(s). Chatterjee, Abhijit; Abraham, Jacob A. ; Issue Date: 1986-10 ; Keyword(s). C-testability; Counters ...

Abstract: This paper investigates the testability of a class of circuits, called counters, that perform the addition of sets of input bits of equal ...

This paper investigates the testability of a class of circuits, called counters, that perform the addition of sets of input bits of equal arithmetic weight.

The testability of a class of circuits called generalized counters is investigated under a more powerful fault model than examined in earlier work.

On the C-Testability of Generalized Counters. This paper investigates the testability of a class of circuits, called counters, that perform the addition ...

It is shown that any generalized counter of full-adder cells is testable for multiple faults with a test set of size proportional to the number of cells.

In this article we discuss a test generation, design-for-testability and built-in self-test methodology for two-dimensional iterative logic arrays (ILAs) ...

Sufficient conditions for C-testability are stated. It is shown that any two-dimensional array can be modified to become C-testable. An extension to systolic ( ...