Results show that the our heuristic is able to increase 3D clock's EM lifetime by more than 3.63x with little wire length overhead, while maintaining zero clock ...

Results show that the our heuristic is able to increase 3D clock's EM lifetime by more than 3.63x with little wire length overhead, while maintaining zero clock ...

Results show that the our heuristic is able to increase 3D clock's EM lifetime by more than 3.63x with little wire length overhead, while maintaining zero clock ...

This paper proposes practically viable clock tree optimization techniques under prebond testability, a TSV-buffer-aware topology generation techniques.

2015. Electromigration-aware clock tree synthesis for TSV-based 3D-ICs. T Lu, A Srivastava. Proceedings of the 25th edition on Great Lakes Symposium on VLSI ...

We propose efficient algorithms to construct a low-power clock tree for through-silicon-via (TSV)-based 3D-ICs. We use shutdown gates to save clock trees' ...

We develop compact EM models for both DC and AC signal nets using detailed finite-element-analysis (FEA) and build EM library for mean-time-to-failure (MTTF).

Low-power and reliable clock network design for through-silicon via (TSV) based 3D ICs. X Zhao, J Minz, SK Lim. IEEE Transactions on Components, Packaging and ...

Electromigration-aware clock tree synthesis for TSV-based. 3D-ICs. In Proc. Great Lakes Symp. VLSI, May. 2015, pp. 27-32. [20] I. Blech et al. Direct ...

Electromigration-aware Clock Tree Synthesis for TSV-based 3D-ICs. Tiantao Lu, Ankur Srivastava. 2015, ACM Great Lakes Symposium on VLSI. Resource Allocation ...