Design-Reuse1y
Implementing Power Management IP for Dynamic and Static Power Reduction in Configurable Microprocessors using the Galaxy Design Platform at 130nm
At 130 nm and 90 nm, power consumption (both dynamic and static) has become a barrier in the roadmap for SoC designs targeting battery powered, mobile applications. This paper presents the results of ...
Design-Reuse10y
A need for static and dynamic Low Power Verification
Fig 1(a): Design state without CPF Fig 1(b): Design state with CPF To ensure that design is compliant with respect to low power constraints defined in CPF, both static and dynamic checks need to be ...