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Given the following clock (clk) and input (D) signals, select the correct output values at the labelled times for a positive level sensitive D latch (+ve level D-1), a positive edge triggered D flip-flop (+ve edge D-ff), and a negative edge triggered D flip-flop (-ve edge D-ff). Note: You can assume all memory elements with initial values of 0. clk (a) (b) (c) (d) (e) Input D T₁ T2 T3 T4 At T1, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 1, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 1, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 1 None of the above

Given the following clock (clk) and input (D) signals, select the correct output values at the labelled times for a positive level sensitive D latch (+ve level D-1), a positive edge triggered D flip-flop (+ve edge D-ff), and a negative edge triggered D flip-flop (-ve edge D-ff). Note: You can assume all memory elements with initial values of 0. clk (a) (b) (c) (d) (e) Input D T₁ T2 T3 T4 At T1, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 1, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 1, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 1 None of the above

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
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Given the following clock (clk) and input (D) signals, select the correct output values at the labelled times for a positive level sensitive D latch (+ve level D-1), a positive edge triggered D flip-flop (+ve edge D-ff), and a negative edge triggered D flip-flop (-ve edge D-ff). Note: You can assume all memory elements with initial values of 0. clk (a) (b) (c) (d) (e) Input D T₁ T2 T3 T4 At T1, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 1, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 1, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 1 None of the above
Transcribed Image Text:Given the following clock (clk) and input (D) signals, select the correct output values at the labelled times for a positive level sensitive D latch (+ve level D-1), a positive edge triggered D flip-flop (+ve edge D-ff), and a negative edge triggered D flip-flop (-ve edge D-ff). Note: You can assume all memory elements with initial values of 0. clk (a) (b) (c) (d) (e) Input D T₁ T2 T3 T4 At T1, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 1, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 0 At T1, +ve level D-1 = 1, +ve edge D-ff = 1, -ve edge D-ff = 0 At T2, +ve level D-1 = 0, +ve edge D-ff = 1, -ve edge D-ff = 0 At T3, +ve level D-1 = 1, +ve edge D-ff = 0, -ve edge D-ff = 0 At T4, +ve level D-1 = 0, +ve edge D-ff = 0, -ve edge D-ff = 1 None of the above
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