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Design the JFET circuit for the largest in swing. Use the self-bias circuit shown in Fig. 6. Assume that VGS (0) = -1.3 and Vcc = 15 volts. Furthermore, assume that ipss = 20 mA. Using Fig. 4b, draw the load line and identify the Q point. Explain why this will allow the largest swing. Use ip = ipss (1- VGS VGS(0) to show what happens to i, and vps when you have a swing of 0.2 volts in vcs form its operating point (that is, change vas by ±0.2 volts and compute the corresponding iD and VDs). RD RG Rs 0 20nA GS=-1.3 VGS 12 10nA -0- Fig. 6. Circuit for Examples 2 &3. BA-C 50 100 150 200 □ ID(J1) UDS Fig. 4b. The IV characteristics of an n-channel JFET (J113). The plots are for VGs increments of 0.05 volts. VGS(0) -1.3. The yellow and blue load lines are for examples 2 &3, respectively.

Design the JFET circuit for the largest in swing. Use the self-bias circuit shown in Fig. 6. Assume that VGS (0) = -1.3 and Vcc = 15 volts. Furthermore, assume that ipss = 20 mA. Using Fig. 4b, draw the load line and identify the Q point. Explain why this will allow the largest swing. Use ip = ipss (1- VGS VGS(0) to show what happens to i, and vps when you have a swing of 0.2 volts in vcs form its operating point (that is, change vas by ±0.2 volts and compute the corresponding iD and VDs). RD RG Rs 0 20nA GS=-1.3 VGS 12 10nA -0- Fig. 6. Circuit for Examples 2 &3. BA-C 50 100 150 200 □ ID(J1) UDS Fig. 4b. The IV characteristics of an n-channel JFET (J113). The plots are for VGs increments of 0.05 volts. VGS(0) -1.3. The yellow and blue load lines are for examples 2 &3, respectively.

EBK ELECTRICAL WIRING RESIDENTIAL
EBK ELECTRICAL WIRING RESIDENTIAL
19th Edition
ISBN:9781337516549
Author:Simmons
Publisher:Simmons
Chapter32: Standby Power Systems
Section: Chapter Questions
Problem 7R: Briefly explain the function of a transfer switch. _____
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Design the JFET circuit for the largest in swing. Use the self-bias circuit shown in Fig. 6. Assume that VGS (0) = -1.3 and Vcc = 15 volts. Furthermore, assume that ipss = 20 mA. Using Fig. 4b, draw the load line and identify the Q point. Explain why this will allow the largest swing. Use ip = ipss (1- VGS VGS(0) to show what happens to i, and vps when you have a swing of 0.2 volts in vcs form its operating point (that is, change vas by ±0.2 volts and compute the corresponding iD and VDs). RD RG Rs 0 20nA GS=-1.3 VGS 12 10nA -0- Fig. 6. Circuit for Examples 2 &3. BA-C 50 100 150 200 □ ID(J1) UDS Fig. 4b. The IV characteristics of an n-channel JFET (J113). The plots are for VGs increments of 0.05 volts. VGS(0) -1.3. The yellow and blue load lines are for examples 2 &3, respectively.
Transcribed Image Text:Design the JFET circuit for the largest in swing. Use the self-bias circuit shown in Fig. 6. Assume that VGS (0) = -1.3 and Vcc = 15 volts. Furthermore, assume that ipss = 20 mA. Using Fig. 4b, draw the load line and identify the Q point. Explain why this will allow the largest swing. Use ip = ipss (1- VGS VGS(0) to show what happens to i, and vps when you have a swing of 0.2 volts in vcs form its operating point (that is, change vas by ±0.2 volts and compute the corresponding iD and VDs). RD RG Rs 0 20nA GS=-1.3 VGS 12 10nA -0- Fig. 6. Circuit for Examples 2 &3. BA-C 50 100 150 200 □ ID(J1) UDS Fig. 4b. The IV characteristics of an n-channel JFET (J113). The plots are for VGs increments of 0.05 volts. VGS(0) -1.3. The yellow and blue load lines are for examples 2 &3, respectively.
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