Consider the amplifier circuit shown below with ẞ = 100 and the input sig is a small sinusoidal signal with DC component being O. +3V Rsig Usig = 2.5 ΚΩ Rc 0 Vo w RE www RL -3 V When the load resistance increases, which of the following statements is true? 0000 The amplification gain is positive and increasing in absolute value. The amplification gain is positive and decreasing in absolute value. The amplification gain is negative and increasing in absolute value. The amplification gain is negative and decreasing in absolute value.

Power System Analysis and Design (MindTap Course List)
6th Edition
ISBN:9781305632134
Author:J. Duncan Glover, Thomas Overbye, Mulukutla S. Sarma
Publisher:J. Duncan Glover, Thomas Overbye, Mulukutla S. Sarma
Chapter5: Transmission Lines: Steady-state Operation
Section: Chapter Questions
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Consider the amplifier circuit shown below with ẞ = 100 and the input sig is a small sinusoidal signal with DC component being O.
+3V
Rsig
Usig
= 2.5 ΚΩ
Rc
0
Vo
w
RE
www
RL
-3 V
When the load resistance increases, which of the following statements is true?
0000
The amplification gain is positive and increasing in absolute value.
The amplification gain is positive and decreasing in absolute value.
The amplification gain is negative and increasing in absolute value.
The amplification gain is negative and decreasing in absolute value.
Transcribed Image Text:Consider the amplifier circuit shown below with ẞ = 100 and the input sig is a small sinusoidal signal with DC component being O. +3V Rsig Usig = 2.5 ΚΩ Rc 0 Vo w RE www RL -3 V When the load resistance increases, which of the following statements is true? 0000 The amplification gain is positive and increasing in absolute value. The amplification gain is positive and decreasing in absolute value. The amplification gain is negative and increasing in absolute value. The amplification gain is negative and decreasing in absolute value.
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